simple exact algorithm for transistor sizing of low-power high-speed arithmetic circuits简单的晶体管尺寸的精确算法高速算术电路低功耗.pdfVIP

Hindawi Publishing Corporation VLSI Design Volume 2010, Article ID 264390, 17 pages doi:10.1155/2010/264390 Research Article Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits Tooraj Nikoubin,1 Poona Bahrebar,2 Sara Pouri,2 Keivan Navi,2 and Vaez Iravani2 1 Faculty of Electrical and Computer Engineering, Shahid Beheshti University, GC, 1983963113, Tehran, Iran 2 Microlectronic Laboratory of Faculty of Electrical and Computer Engineering, Shahid Beheshti University, GC, 1983963113, Tehran, Iran Correspondence should be addressed to Tooraj Nikoubin, t nikoubin@sbu.ac.ir Received 23 May 2009; Revised 8 October 2009; Accepted 21 January 2010 Academic Editor: Wieslaw Kuzmicz Copyright © 2010 Tooraj Nikoubin et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. A new transistor sizing algorithm, SEA (Simple Exact Algorithm), for optimizing low-power and high-speed arithmetic integrated circuits is proposed. In comparison with other transistor sizing algorithms, simplicity, accuracy, independency of order and initial sizing factors of transistors, and flexibility in choosing the optimization parameters such as power consumption, delay, Power- Delay Product (PDP), chip area or the combination of them are considered as the advantages of this new algorithm. More exhaustive rules of grouping transistors are the main trait of our algorithm. Hence, the SEA algorithm dominates some major transistor sizing metrics such as optimization rate, simulation speed, and reliability. According to approximate comparison of the SEA algorithm with