on the design with cpld（与cpld的设计）.docVIP

On the design with CPLD [Keywords] design, conduct, devices, based on, CPLD, architecture, Keywords: CPLD; FPGA, ASIC, I / O expansion CPLD is how to define it? There are several characteristics of the device is a CPLD can be defined rather than FPGA. Most designers agree that the CPLD device must be embedded non-volatile memory to provide accelerated single-chip solution. In addition, the timing must be fast point to point, or lower to be in the range of 5ns. There are other standards, the CPLD through the consideration of different architectural approaches to achieve a better understanding of these standards. Traditionally, through a number of wide (multi-input) and (AND) entry form or (OR) function to implement CPLD, these items often referred to with the product terms (PT). Each or combination of features and associated registers and register, or gate often referred to as the PT and its associated macrocell. LatticeispMACH4000 CPLD is used in this typical architecture. this particular logical architecture provides a fast and simple timing analysis, this feature is usually referred to as deterministic. Figure 1 shows the PT-based The CPLD architecture diagram. In recent years, improved silicon process technology and advanced design software tool to generate a new look-up table-based (LYT) of the CPLD, as shown in Figure 2. LUT-based devices can provide the speed and timing certainty, and in the past Only the PT-based architecture with these characteristics in the LUT-based devices, the typical 4-input LUT and registers together form the basic logical unit. This combination is often referred to as LUT. typical example of this architecture can LatticeMachXO to find. A typical CPLD applications In a large number of applications, CPLD device can achieve a variety of functions. CPLD device can be the four most common application is as follows: Reset Logic Most systems have a small amount of logic in the receive signal before powe