RISCReduced Instruction Set Architecture精简指令集架构.pptVIP

RISC:Reduced Instruction Set Computing Overview What is RISC architecture? How did RISC evolve? How does RISC use instruction pipelining? How does RISC use register windowing? What is the future of RISC ? Early Microprocessors Early Microprocessors were very simple They had a small instruction set Gradually, more and more instructions were added CISC: Complex Instruction Set Computing May include over 300 instructions Approximately a 1:1 relationship with higher level languages Only some of these instructions are used all the time Why are more instructions slower ? A 16 instruction set uses a 4 to 16 decoder If you had a 32 instruction set, you would have to use a 5 to 32 decoder The larger the decoder, the longer the propagation delay Problem with CISC The more instructions in the instruction set, the larger the propagation delay CISC is too slow Get rid of some of those Instructions It takes 20 ns to complete each instruction If we reduce the instruction set, we can get it down to 18 ns to complete each instruction Every instruction we deleted can be replaced by 3 of the simpler remaining instructions We choose to eliminate instructions used less than 2% of the time Consider This 100%(20 c) vs. 98% (18c) + 2%(54c) =20c vs. 17.64c + 1.08 c 20c 18.72c In this case, reducing instructions is faster Don’t reduce too much - say we eliminate instructions used 10% of the time 100%(20 c) vs. 90% (18c) + 10%(54c) =20c vs. 16.2c + 5.4 c 20c 21.6c If we reduce our instruction set too much, the end result could be slower RISC: Reduced Instruction Set Architecture Fewer than 100 instructions in instruction set Fixed Length Instructions Limited Loading and Storing instructions Fewer Addressing modes Instruction Pipeline Large number of registers RISC:Reduced Instruction Set Architecture cont. Hardwired control unit Delayed loads and branches Speculative Execution of Instructions Optimizi