97和53离散小波变换可重构硬件实现 word格式.docx

AbstractThis thesis firstly introduces research background, focuses my research in DWT(Discrete Wavelet Transform)algorithm of the still image compression in JPEG2000. Then a reconfigurable hardware structure is presented to implement the DWT algorithm. Next, we use Lena image to examine one dimension and two dimention system, which include folded structure.We import standard image in Jasper software, pre-process the data, then use DWT hardware, next we use Jasper again.It means we replace the DWT part in Jasper by our hardware design.Finally, we use FPGA system self-developed by Fudan university to verify our design.Generally, the main contribution and creative work are listed in this thesis: (1)Give an effective solution to determine data width in DWTIn chapter four, how to express floating point numbers is concerned in DWT based on lifting scheme. On the one side, data must not overflow and have enough precision, so bigger bit width is needed.on the other side, we hope smaller width to reduce caiculation, this means smaller circuit area.So, there is a tradeoff in bit width choice.It is well hnown PSNR is evaluation standard in image process and reconstruction. We adopt some standard image, such as Lena, Cameraman, Boat, Cri, etc. analysis different PSNR in different width, image and compression ratio. By this mean, we can choose a proper width.Design tree type multiplierIn chapter four, we design pipeline folded structure to improve frequency. How to design muitifier is a critical step. Firstly, lifting factors are expressed as CSD number. Secondly, Horner principle is adopted. Finally, tree type muitipliers are designed.Design 2-D DWT structure included reconfigurable circuitIn chapter five, 2-D DWT structure included reconfigurable circuit is designed, whose scanning manner is line-based.In row’s and column’s DWT, folded structure isused.Verifing the design with FPGA system of Fudan UniversityIn chapter five, hardware design is verified with FDP250K and FDE2007