Chapter 5 Assembly Language TI C5000官方教材.ppt

Status bit Set/Clear ? When these instructions are decoded to modify status bit CAFRZ (15), CAEN (14), or CACLR (13), the CPU pipeline is flushed and the instruction is executed in 5 cycles regardless of the instruction context. Extended auxiliary register (XAR) operations Logical operations Logical operations Logival operations Miscelaneous operations Move operations Move operations Move operations Some examples for the 17 forms of ADD ADD uns(*AR3) #31, AC1, AC0 The unsigned content addressed by AR3 shifted left by 31 bits is added to the content of AC1 and the result is stored in AC0. ADD dbl(*AR3+), AC1, AC0 The content (long word) addressed by AR3 and AR3 + 1 is added to the content of AC1 and the result is stored in AC0. Because this instruction is a long-operand instruction, AR3 is incremented by 2 after the execution. ADD *AR3, *AR4, AC0 The content addressed by AR3 shifted left by 16 bits is added to the content addressed by AR4 shifted left by 16 bits and the result is stored in AC0. ADD #FFFFh, *AR3 The content addressed by AR3 is added to a signed 16-bit value and the result is stored back into the location addressed by AR3. ADDV AC1, AC0 The absolute value of AC1 is added to the content of AC0 and the result is stored in AC0. Arithmetic instructions: compare and select extremum See examples and more details on next slides Index Search - DMAXDIFF, MAXDIFF DMAXDIFF ACx,ACy,ACz,ACw,TRNx 32-bit Search ACx/ACy = values, ACz = max, ACw = ACy-ACx, TRNx = index ~N cycles for N taps with index TRN0/1 0 15 1 (If new max, shift “1” into MSB) Splits AC’s into two 16-bit registers Max of hi/low halves placed in ACz, ACy-ACx placed in ACw, TRN0/1 hold index TRN0 (tracks AC high), TRN1 (tracks AC low) ~N/2 cycles for N taps with index MAXDIFF ACx,ACy,ACz,ACw Dual 16-bit Search MINDIFF and DMINDIFF also supported Example of MAXDIFF instruction MAXDIFF AC0, AC1, AC2, AC1 Before After AC0 10 2400 2222 AC0 10 2400 2222 AC1 90 0000 0000 AC1 FF 8000 DDDE AC2