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UCSD VLSI CAD Laboratory – SLIP 2011 UCSD VLSI CAD Laboratory – SLIP 2011 Stability and Scalability in Global Routing S. K. Han1, K. Jeong1, A. B. Kahng1,2 and J. Lu2 1ECE Department, UC San Diego 2CSE Department, UC San Diego System-Level Interconnect Prediction Workshop June 5, 2011 UCSD VLSI CAD Laboratory – SLIP 2011 * Outline Motivation Routing Estimation Experiments Conclusions UCSD VLSI CAD Laboratory – SLIP 2011 * UCSD VLSI CAD Laboratory – SLIP 2011 * Motivation: Evaluation of Routability Routability: whether a placed design is routable? Must avoid unroutable placement results Loop back to placement after routing fails == too expensive! Routability determination during placement is critical but difficult Built-in congestion estimators in modern placers Placement Result Routing Result UCSD VLSI CAD Laboratory – SLIP 2011 * Congestion Estimation During Placement Static, non-constructive Fixed L-Z shape models Equal-probability models #bends-based probabilistic models Testcase-independent models ? too wide a gap between estimates and actual routing outcomes Constructive Integrated global router (under the hood of placement tool) Helps PR convergence ? global router must be high-quality and fast to serve in this role This Work How good can a routing estimator be? One way to answer this question: How noisy or inherently unpredictable is the routing (or, router) that we’re trying to estimate? We experimentally access “inherent unpredictability”: Routing grid offset noise Routing resource noise Routing instance scaling We discover stability, scalability limits of global routers UCSD VLSI CAD Laboratory – SLIP 2011 * Testbed (based on ISPD Global Routing Contest) Routing quality metrics TOF (total overflow) MOF (maximum gedge-overflow) WCI(A) (Worst congestion index) U(A) (Average net-score) ISPD-2008 Global Routing Benchmark Suite Four academic global routers FastRoute-4.1 NTHU-2.0 FGR-1.2 NTUgr-1.1 UCSD VLSI CAD Laboratory – SLIP 2011 * Experiment
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