基于FPGA图像超分辨率硬件化实现.docVIP

基于FPGA图像超分辨率硬件化实现 　　摘 要： 设计基于FPGA的图像超分辨率双线性插值实现方式，提出基于单输入双输出端口RAM缓冲的二级循环调度机制，用以实现共享资源分配和并行流水处理。单输入双输出端口的RAM实现读取相邻地址的两个数据，RAM的深度为源图像一行的像素点数，宽度为像素数据宽度，实现源数据相邻两行像素的存储。根据位置分析模块得到源图像的位置，将源图像的数据写入相应RAM中进行加权运算。为了提高效率使用乒乓算法，设计了4个RAM，2个RAM为一组，一组RAM在加权运算时，另一组RAM写入数据。该设计在Kintex?7开发板上得到验证，实现图像处理速度达到25～30 f/s，同时图像插值后不仅细节更加清晰，从直方图中可以看到图像得到了均衡化。 　　关键词： FPGA； 超分辨率； 双线性插值； 循环调度 　　中图分类号： TN911.73?34； TP391 文献标识码： A 文章编号： 1004?373X（2017）17?0044?03 　　FPGA?based hardware implementation of image super?resolution 　　ZHONG Xueyan1， XIA Qianliang2， CHEN Zhijun3 　　（1. Nanjing Institute of Railway Technology， Nanjing 210031， China； 2. CETC Deqing Huaying Electronics Co.， Ltd.， Huzhou 313200， China； 　　3. Nanjing University of Aeronautics and Astronautics， Nanjing 211106， China） 　　Abstract： An FPGA?based implementation mode of image super?resolution bilinear interpolation was designed. A two?stage round?robin scheduling mechanism based on RAM with single?input and dual?output port is proposed to realize the shared resource allocation and parallel pipeline processing. RAM with single?input and dual?output port can read two data whose address are adjacent. The quantity of pixels within a row in source image is deemed as the depth of RAM， and the width of pixel data is deemed as that of RAM to store the two rows of pixels adjacent to the source data. The position of source image is gotten according to the position analysis module. The data of source image is written into the corresponding RAM for weighting operation. In order to improve the efficiency， the ping?pong algorithm is adopted to design four RAMs which are divided into two groups （each one includes two RAMs）. If one group of RAMs is performed with weighting calculation， another group of RAMs is performed with data write?in. The design was verified on Kintex?7 development board， which can process the image with the speed of 25～30 f/s. The interpolated image has clear detail. The image is equalized， which is shown in histogram.