译码器quretus II仿真教程.pdfVIP

3-8 验3-8 译码验 Quartus II Verilog DE0 ——3-8 Quartus 3.1 Quartus 1. Quartus II 2-1 11 208 3-8 1-1 Quartus II 2. File-New Project Wizard 1-2 1-2 New Project Wizard Wizard 1-3 Next 12 208 3-8 1-3 New Project Wizard 3. 2-4 Next 1-4 13 208 3-8 4. 1-5 .v Next 1-5 5. Altera DE0 DE0 FPGA Family Cyclone IIPackage FBGAPin Count 484Speed grade 6Available devices EP3C16F484C61-6 1-6