计算机组织与结构：13_RISC_8.pptVIP

William Stallings Computer Organization and Architecture8th Edition Chapter 13 Reduced Instruction Set Computers Chapter 13Reduced Instruction Set Computers Key terms Key points Chapter titles Chapter 13Reduced Instruction Set Computers Key terms CISC complex instruction set computer RISC reduced instruction set computer Delayed branch Delayed load HLL high-level language Register file Register window SPARC Major Advances in Computers(1) The family concept IBM System/360 1964 DEC PDP-8 Separates architecture from implementation Microporgrammed control unit Idea by Wilkes 1951 Produced by IBM S/360 1964 Cache memory IBM S/360 model 85 1969 Major Advances in Computers(2) Solid State RAM (See memory notes) Microprocessors Intel 4004 1971 Pipelining Introduces parallelism into fetch execute cycle Multiple processors The Next Step - RISC Reduced Instruction Set Computer Key features Large number of general purpose registers or use of compiler technology to optimize register use Limited and simple instruction set Emphasis on optimising the instruction pipeline Comparison of processors Driving force for CISC Software costs far exceed hardware costs Increasingly complex high level languages Semantic gap Leads to: Large instruction sets More addressing modes Hardware implementations of HLL statements e.g. CASE (switch) on VAX Semantic: 语义的;语义学的 Gap 英音：[g?p] 豁口,裂口 Intention of CISC Ease compiler writing Improve execution efficiency Complex operations in microcode Support more complex HLLs ease 减轻 HLL 缩写词 abbr.  high-level language 【电脑】高级语言 Execution Characteristics Operations performed Operands used Execution sequencing Studies have been done based on programs written in HLLs Dynamic studies are measured during the execution of the program Operations Assignments Movement of data Conditional statements (IF, LOOP) Sequence control Procedure call-return is very time consuming Some HLL instruction lead to many machine code operations Assi