VHDL与数字集成电路设计VHDL7-1.pptVIP

2021/3/14 * Longest Logic Path in Edge-Triggered Systems Clk T TSU TClk-Q TLM Latest point of launching Earliest arrivalof next cycle TJI + d 2021/3/14 * Clock Constraints in Edge-Triggered Systems If launching edge is late and receiving edge is early, the data will not be too late if: Minimum cycle time is determined by the maximum delays through the logic Tc-q + TLM + TSU T – TJI,1 – TJI,2 - d Tc-q + TLM + TSU + d + 2 TJI T Skew can be either positive or negative 2021/3/14 * Shortest Path Clk TClk-Q TLm Earliest point of launching Data must not arrivebefore this time Clk TH Nominalclock edge 2021/3/14 * Clock Constraints in Edge-Triggered Systems Minimum logic delay If launching edge is early and receiving edge is late: Tc-q + TLM – TJI,1 TH + TJI,2 + d Tc-q + TLM TH + 2TJI+ d 2021/3/14 * Clock Distribution Clock is distributed in a tree-like fashion H-tree 2021/3/14 * More realistic H-tree [Restle98] 2021/3/14 * The Grid System No rc-matching Large power 2021/3/14 * 21164 Clocking 2 phase single wire clock, distributed globally 2 distributed driver channels Reduced RC delay/skew Improved thermal distribution 3.75nF clock load 58 cm final driver width Local inverters for latching Conditional clocks in caches to reduce power More complex race checking Device variation trise = 0.35ns tskew = 150ps tcycle= 3.3ns Clock waveform Location of clock driver on die pre-driver final drivers 2021/3/14 * 2021/3/14 * Clock Skew in Alpha Processor 2021/3/14 * 2 Phase, with multiple conditional buffered clocks 2.8 nF clock load 40 cm final driver width Local clocks can be gated “off” to save power Reduced load/skew Reduced thermal issues Multiple clocks complicate race checking trise = 0.35ns tskew = 50ps tcycle= 1.67ns EV6 (Alpha 21264) Clocking 600 MHz – 0.35 micron CMOS Global clock waveform 2021/3/14 * Synchronous Pipelined Datapath 2021/3/14 * Self-Timed Pipelined Datapath 2021/3/14 * Hand-Shaking Protocol Two Phase Handshake 2021/3/14 * Event Logic – The Mulle