基于FPGA的卷积神经网络设计与实现.docx

PAGE 17 摘要 计算机和信息技术的飞速发展，使得人工智能被推上了全新高度，神经网络作为人工智能中较为重要的一环，在目前很多领域均在使用，尤其是一些仅需要重复几种动作或固定形式的场景下，被使用的更加频繁。卷积神经网络是发明较早且技术较为成熟的一种神经网络算法，但在当今社会仍然是主流算法，因此，本文将通过FPGA来实现对卷积神经网络算法的加速。选择FPGA来实现加速是由于FPGA的可重复编程且编程灵活的特性，在具有强大的处理能力时功耗较低，因此这就为实现加速提供了无限的可能。 为了实现本文加速，在编程上分别对各个模块进行功能的实现，然后将各模块在顶层模块中进行统一调用，这也符合设计思路，当各模块均正常工作后才能保障系统能够正常运行。本文在各个模块实现的过程中均通过Modesim进行了时序仿真，设计语言均选择Verilog HDL语言，通过对时序图和硬件实物的功能测试，可以看出本文设计的基于FPGA的卷积神经网络系统的设计达到了设计要求，其准确率可到98.11%。 关键词：卷积神经网络；FPGA；并行性；Modesim  Abstract The rapid development of computer and information technology has pushed artificial intelligence to a new level. As a more important part of artificial intelligence, neural networks are currently used in many fields, especially those that only need to repeat several actions or fixed forms. It is used more frequently in the scenario. Convolutional neural network is a neural network algorithm that was invented earlier and with more mature technology, but it is still the mainstream algorithm in todays society. Therefore, this article will use FPGA to realize the acceleration of the convolutional neural network algorithm. Choosing FPGA to achieve acceleration is due to its reprogrammable and flexible programming characteristics, and low power consumption when it has powerful processing capabilities, so this provides unlimited possibilities for achieving acceleration. In order to speed up this article, the functions of each module are implemented separately in programming, and then each module is called uniformly in the top-level module. This is also in line with the design idea. The normal operation of the system can be ensured when each module is working normally. In this paper, in the process of implementing each module, the timing simulation is performed through Modesim. The design language is Verilog HDL. Through the functional test of the timing diagram and the hardware, it can be seen that the FPGA-based convolutional neural network system designed in this paper is effective The design meets t