计算机组成与结构：chapter15 The IA-64 Architecture.pptVIP

Computer Organization ArchitectureChapter 15The IA-64 Architecture 15.1 Motivation64-bit processor developed by Intel and HP Basic concepts underlying IA-64 refers to as explicitly parallel instruction computing (EPIC)Explicit instruction-level parallelismLong and very long instruction wordsBranch predicationSpeculative loadingSoftware pipeliningItanium is first Intel productTable 15.1 gives us key differences between IA-64 and a normal superscalar Superscalar vs. IA-64 New ArchitectureNot hardware compatible with x86Now have tens of millions of transistors available on chipCould build bigger cacheDiminishing returnsAdd more execution units Increase superscalaring“Complexity wall”More units makes processor “wider”More logic needed to orchestrateImproved branch prediction requiredLonger pipelines requiredLarger number of renaming registers requiredAt most six instructions per cycleGreater penalty for misprediction Explicit ParallelismInstruction parallelism scheduled at compile timeIncluded with machine instructionProcessor uses this info to perform parallel executionRequires less complex circuitry for parallel schedulingCompiler has much more time to determine possible parallel operationsCompiler sees whole program 15.2 General OrganizationA generous number of registers256 registers128 for integer,logical,and general-purpose use128 82bit for FPs and graphics use64 1-bit predicate registersUsed for predicate executionTo support high degree of parallelismMultiple execution units8 or more parallel unitsSee fig.15.1 General Organization for IA-64 IA-64 Execution UnitsI-UnitInteger arithmeticShift and addLogicalCompareInteger multimedia opsM-UnitLoad and storeBetween register and memorySome integer ALUB-UnitBranch instructionsF-UnitFloating point instructions 15.3 Predication, speculation and software pipelingInstruction Format128-bit bundle: 3 instructions and a template fields, see fig.15.2The processor can fetch one bundle at a timeTemplate field contains informatio