计算机组成与结构：chapter16 Control Unit Operation.pptVIP

Computer Organization ArchitectureChapter 16Control Unit Operation 16.1 Micro-OperationsA computer executes a program in many instruction cycles, typically, an instruction/cycleFetch/execute sub-cyclesEach sub-cycle has a number of stepsThese steps are called micro-operations, see Fig.16.1Each step is simple and does very little, atomic operation of CPUMicro-operations are the atomic operations of a processor Constituent Elements of Program Execution Fetch CycleAccess PC, PC contains address of next instructionAddress moved to MARAddress placed on address busControl unit requests memory readResult placed on data bus, copied to MBR Then, to IRMBR is now free for further data fetchesMeanwhile PC incremented by I(in parallel with data fetch from memory) Fetch Sequence (symbolic)t1: MAR ? (PC)t2: MBR ? (memory) PC ? (PC) +It3: IR ? (MBR)(tx = time unit/clock cycle, a clock pulse)t1: MAR ? (PC)t2: MBR ? (memory)t3: PC ? (PC) +I IR ? (MBR) Sequence of Events, Fetch Cycle1 Rules for Clock Cycle GroupingProper sequence must be followedMAR ? (PC) must precede MBR ? (memory)Conflicts must be avoidedCan not read write same register at same timeMBR ? (memory) IR ? (MBR) must not be in same cycleAlso: PC ? (PC) +I involves additionUse ALUMay need additional micro-operations Indirect Cyclet1: MAR ? (IRaddress) - address field of IRt2: MBR ? (memory)t3: IRaddress ? (MBRaddress)MBR contains an address for operandIR is now in same state as if direct addressing had been used Data Flow -- Indirect Diagram Interrupt Cyclet1: MBR ?(PC)t2: MAR ? save-address PC ? routine-addresst3: memory ? (MBR)This is a minimumMay be additional micro-ops to get addressesNote, saving context is done by interrupt handler routine, not micro-ops Execute CycleDifferent for each instructione.g. ADD R1,X add the contents of location X to Register 1 , result in R1t1: MAR ? (IRaddress)t2: MBR ? (memory)t3: R1 ? R1 + (MBR) Exe