ASIC仿真加速系统编译优化策略研究.docVIP

ASIC仿真加速系统编译优化策略研究 　　摘要：随着微处理器设计技术的发展，基于硬件仿真加速器的系统验证已成为业内公认的最有效的系统验证方法，而系统仿真频率是硬件仿真加速器验证系统最重要的性能指标之一.本文以某款国产高性能通用微处理器FT-xx在ASIC仿真加速平台上的系统仿真加速为工程背景，通过调整编译选项、分析编译结果展开研究.首先分析了ASIC硬件仿真加速的加速原理，然后重点研究了逻辑资源数量、通用寄存器类型设计映射方式、特殊寄存器类型设计映射方式对系统仿真频率的影响.研究结果表明，当待验证设计的规模一定时，ASIC仿真器的逻辑资源并非越多越好、memorysize值的选取存在一个较佳范围、对于某些特殊的寄存器采用强制映射能极大地提高系统仿真频率. 　　关键词：硬件仿真加速器；ASIC；频率；仿真加速 　　中图分类号：TP302.1 文献标识码：A 　　An Effective Memory System Verification Method Based 　　on ASIC Emulation Acceleration System 　　ZHOU Hai-liang， BAI Ying， ZHANG Shun， LUO Li 　　（College of Computer， National Univ of Defense Technology， Changsha， Hunan 410073， China） 　　Abstract： With the development of microprocessor， emulation accelerator based verification has become the most effective system verification method. And the system frequency is one of the most important indexes of the emulation acceleration system. Based on the engineering application of the system verification to a homemade high performance microprocessor FT-X on a ASIC emulator， research was done by tuning the compile parameters assisted with compile results analysis. The acceleration mechanism of ASIC accelerator was analyzed. And then， the effect of domain number， normal register design mapping method， special register design mapping method on the system emulation frequency was studied. The results show that its not a good idea to increase the domain number as much as possible， because there exists a sound range of memory size when the design under test is fixed. And the system emulation frequency was increased sharply by the application of forcible mapping method to some special blocks on the other hand. 　　Key words： hardware acceleration system； ASIC； frequency； emulation acceleration 　　随着处理器技术的飞速发展，微处理器设计规模的增大，处理器设计已达上亿逻辑门规模.如此大规模的集成电路设计给系统验证带来了极大的挑战[1-2].传统的基于功能检测、模拟测试等软件测试方法所花费的时间骤升到以天为单位，已成为影响产品上市时间的最大瓶颈，这是企业在竞争日益激烈的今天越发难以承受的[3].即使是日益流行的IP复用技术，传统的硬件描述语言（Hardware Description Language，HDL）仿真器也难以胜任.而且越来越多的应用需要大量实时数据的处理（如视频等），这就要求验证环境具有接近真实系统的