cpuled计算机组成实验.docVIP

module alu(s,sel,cin,wt,d,f,cout,x,y,clk); input sel,wt,cin,clk; input [2:0] s; input [7:0] d; output reg [7:0] f,y; output reg [2:0] x; output cout; reg [7:0] a,b; initial begin a=0; b=0; end always @(posedge clk) begin if(sel==1wt==1) a=d; else if(sel==1wt==0) b=d; case(s) 3b000:f=0; 3b001:f=ab; 3b010:f=a|b; 3b011:f=a^b; 3b100:{cout,f}=a+b+cin; 3b101:f=a1; 3b110:f=a1; 3b111:f=8hzz; endcase end always @(posedge clk) begin x=3b000; xianshi(x,f[7:4]); x=3b001; xianshi(x,f[3:0]); end task xianshi ; input[2:0] ax; input[3:0] af; case(af[3:0]) 4d0:y=8 4d1:y=8 4d2:y=8 4d3:y=8 4d4:y=8 4d5:y=8 4d6:y=8 4d7:y=8 4d8:y=8 4d9:y=8 4d10:y=8 4d11:y=8 4d12:y=8 4d13:y=8 4d14:y=8 4d15:y=8 endcase endtask endmodule module cpu(d,ra,wr,rd,m,clk,clk1,reset,ale,pcl,pch,x,y); input wr,rd,clk,reset,ale,clk1; input [1:0] ra,m; input [7:0] d; output reg [7:0] pcl,pch,y; output reg [2:0] x; reg [7:0] r0,r1,r2,r3; reg [15:0] pc; initial begin x=0; y=0; pcl=0; pch=0; pc=0; r3=0; r0=0; r1=0; r2=0; r3=0; end always@(negedge clk) //8位寄存器 begin begin if(wr==0rd==1) case(ra) 2b00:r0=d; 2b01:r1=d; 2b10:r2=d; 2b11:r3=d; endcase else if(wr==1rd==0) case(ra) 2b00:pcl=r0; 2b01:pcl=r1; 2b10:pcl=r2; 2b11:pcl=r3; endcase end if(ale==1)pcl=pc[7:0]; pch=pc[15:8]; end always@(negedge clk1) //16位寄存器 begin if(reset==0)pc=0; else case(m) 2b00:pc[15:8]=d; 2b01:pc[7:0]=d; 2b10:pc=pc+1; 2b11:pc=pc-1; endcase end always@(negedge clk) begin x=x+1; if(x==0) xianshi(pch[7:4]); else if(x==1) xianshi(pch[3:0]); else if(x==2) xianshi(pcl[7:4]); else if(x==3) xianshi(pcl[3:0]); else xianshi(0); end task xianshi ; input[3:0] af; case(af[3:0]) 4d0:y=8 4d1:y=8 4d2:y=8 4d3:y=8 4d4:y=8 4d5:y=8 4d6:y=8 4d7:y=