cpuled计算机组成实验.docVIP

module alu(s,sel,cin,wt,d,f,cout,x,y,clk); input sel,wt,cin,clk; input [2:0] s; input [7:0] d; output reg [7:0] f,y; output reg [2:0] x; output cout; reg [7:0] a,b; initial begin a=0; b=0; end always @(posedge clk) begin if(sel==1wt==1) a=d; else if(sel==1wt==0) b=d; case(s) 3b000:f=0; 3b001:f=ab; 3b010:f=a|b; 3b011:f=a^b; 3b100:{cout,f}=a+b+cin; 3b101:f=a1; 3b110:f=a1; 3b111:f=8hzz; endcase end always @(posedge clk) begin x=3b000; xianshi(x,f[7:4]); x=3b001; xianshi(x,f[3:0]); end task xianshi ; input[2:0] ax; input[3:0] af; case(af[3:0]) 4d0:y=8 4d1:y=8b0