面向逻辑设计SDRAM 控制器性能度量模型.docVIP

面向逻辑设计SDRAM 控制器性能度量模型 　　摘 要:以SDRAM控制器为研究对象,探讨硬件逻辑设计时其性能度量的方法,通过建立一个硬件时钟周期级上的SDRAM控制器性能度量模型,在硬件逻辑实现的层次上实现了SDRAM控制器性能的评估。根据该性能度量模型,既可以分析已有设计的性能,又可以启发SDRAM控制器的优化方案。在双向有线数字电视信道SoC系统平台上应用该度量模型对三个AMBA总线接口的SDRAM控制器实现方案的性能进行分析,从而验证该性能度量模型适用于评估和指导SDRAM控制器的设计。该实验方法还可以用来评价各个不同IP核提供商提供的SDRAM控制器IP核,以及评估SoC系统中一些其他IP核的性能。依据模型给出的量化分析信息,对优化设计具有启发性。 　　关键词:SDRAM控制器; 性能度量; 逻辑设计; 片上系统; IP核; AMBA总线 　　中图分类号:TP393文献标志码:A 　　文章编号:1001-3695(2009)09-3432-04 　　doi:10.3969/j.issn.1001-3695.2009.09.065 　　 　　Metrics and its verification for SDRAM controllerperformance analysis specified for logic design 　　PAN Guang-rong, WANG Qin, QI Yue, YU Mei-qiang 　　(School of Information Engineering, University of Science Technology Beijing, Beijing 100083, China) 　　Abstract:Based on the platform of two-way cable networked SoC, this paper focused on how to evaluate the performance of a SDRAM controller during the stage of the hardware logic design, and gave an accurate cycle-level model for SDRAM controller performance analysis, which enabled the performance evaluation at the logic design level of a SDRAM controller. The metrics could be used to analyze the performance of a designed SDRAM controller and illumine optimized design for SDRAM controllers. Validated this model by exploiting it to analyze the performance of three different SDRAM controllers, so that proved the model to be capable of evaluating and guiding the design of a SDRAM controller.The method could also be used to analyze the performance of other IP cores in a SoC system and to select the proper SDRAM controller IP core if it was more efficient to buy one rather than design one in person. By qualitative analysis according to the model, some heuristic information can be given to guide performance optimization. 　　Key words:SDRAM controller; performance metrics; logic design; SoC(system on chip); IP core; AMBA bus 　　 　　很多SoC(system on chip)系统的外部存储部件均采用SDRAM(synchronous dynamic RAM)。DRAM在PC、工作站平台上的广泛应用使其性能分析成为一个关键问题[1,2]。同样,SDRAM在