VerilogHDL实验串行数据检测.docxVIP

0妥郵電參院 Verilog HDL实验报告（六） 系部名称： 通信工程 专业名称： 通信工程 班 级： 班内序号: 学生姓名: 实验内容：串行数据检测 设计模块 源代码： module check(clk,rst,in,out); input clk,rst; input in; output out; reg [3:0] state; reg out; parameter idle=3b000, state 1 =3*5001, state2=3,b010, state3=3b011, state4=3,bl00, state5=3bl01, state6=3,bll0, state7=3!bl 11; always @(posedge elk or negedge rst) 讦(!rst) begin state=idle; end else case (state) idle: if(in=rbO) state=statel; else state=idle; state 1: if(in==lbl) state=state2; else state=state 1; state2: if (in=Tbl) state3: state=state3; else state=state 1; if(in==rbO) state=state4; else state=idle; state4: if(in__ fbl) state=state5; state5: else state=statel; if(in==lbO) state=state6; else state=state3; state6: if (in==lbl) state=state7; else state=statel; state7: state=idle; default: state=idle; endcase always @ (posedge elk or negedge rst) begin if(!rst) out=TbO; else if (state==state7) out=Tbl; else out=rbO; end endmodule 二测试模块 module jiance; reg elk,rst; reg [23:0]in; wire out; wire [2:0]state; wire x,z; check we(clk,rst,in,out); assign x=in[23]; always #10 clk=?clk; always @(posedge elk) in={ in[22:0],in[23]}; initial begin $monitor($time ,nout=%bH,out); clk=0; rst=l; #2 rst=O; #50 rst= 1; #50 rst=O; in^WOll 1111 1110 0101 1010; #500 $stop; end endmodule 三输出结果 刊0卄 平啊应 0卄 1 餐宓［. 刖0廿 m^z f 桐/^ r