82时序电路的设计计数器chenyu1.ppt

? Review of the last class 8.4.3 MSI Counters and Applications 4 位二进制计数器 74x163 74x163 的功能表 0 1 1 1 1 ? ? CLK 工作状态 同步清零 同步置数 保持 保持 , RCO=0 计数 CLR_L LD_L ENP ENT ? 0 1 1 1 ? ? ? ? 0 1 ? 0 1 1 74x161 异步清零 Connections for the 74X163 to operate in a free-running mode(P715) 74x163 工作于自由运行模式时的接线方法 A free running divide-by-16 counter 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 a free-running 163 can be used as a divide-by-2, -4, -8, or -16 counter, by ignoring any unnecessary high-order output bits. Other MSI counters ? 1bit BCD counter ? 74x160 Synchronous clear 、 ? 74x162 A synchronous clear 0 1 2 3 4 5 6 7 8 9 0 QA QB QC QD 74x160 、 74x162 ? the counting sequence is modified to go to state 0 after state 9. In other words, these are modulo-10 counters, sometimes called decade counters . ? the QD and QC outputs have one-tenth of the CLK frequency, they do not have a 50% duty cycle, and the QC output. Other MSI counters ? 74x169---up/down counter UP/DN UP/DN = 1 counts up （ 升序） UP/DN = 0 counts down （降序） Enable inputs ripple carry out Active-low A B C G1 G2A G2B Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 74x138 EN1 EN2_L EN3_L SRC0 SRC1 SRC2 P0 P1 P7 SDATA 如何控制地址端自动 轮流选择输出 Y 0 ～ Y 7 —— application of the counter Timing diagram for a modulo-8 binary counter and decoder, showing decoding glitches. 若在一次状态转移中有 2 位或多位计数位同时变化， 译码器输出端可能会产生“尖峰脉冲” —— 功能性冒险 0 1 2 3 4 5 6 7 0 1 2 CLK 8- bit register More better way 。。。 A modulo-8 binary counter and decoder with glitch-free ( 无尖峰 ) outputs. Ring counter Modulo-m counter ? Use SSI device —— Clocked Synchronous State-Machine Design ? Use MSI counter —— using n bit binary counter as a modulo-m counter in two cases ： m 2 n m 2 n Although the 163 is a modulo-16 counter, it can be made to count in a modulus less than 16 by using the CLR_L or LD_L input to shorten the normal counting sequence. 电路 ? using the 163 as a modulo-11 counter ( 用 4 位二进制计数器 74x163 实现模 11 计数器 ) ? 清零法 S0 S1 S2 S3 S4 S12 S11 S10 S9 S8 S7 S6 S5 S13 S14