EDA作业的参考答案.pdfVIP

3.3 参考答案 （以下答案不是唯一，可以有不同的描述） library ieee; use ieee.std_logic_1164.all; entity MUXA is port(a1,a2,a3 :in std_logic; s0,s1 :in std_logic; outy :out std_logic ); end entity MUXA; architecture mu of MUXA is signal tmp :std_logic; begin process(a2,a3,s0) begin case s0 is when 0= tmp=a2; when 1= tmp=a3; when others =null; end case; end process; process(a1,tmp,s1) begin case s1 is when 0= outy=a1; when 1= outy=tmp; when others =null; end case; end process; end architecture mu; 3.7 参考答案 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY H_SUBER IS PORT ( X, Y : IN STD_LOGIC; DIFF : OUT STD_LOGIC; S_OUT : OUT STD_LOGIC ); END H_SUBER; ARCHITECTURE ONE OF H_SUBER IS SIGNAL XY, DS : STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN XY = X Y; DIFF = DS(1); S_OUT = DS(0); PROCESS (XY) BEGIN CASE (XY) IS WHEN 00 = DS = 00; WHEN 01 = DS = 11; WHEN 10 = DS = 10; WHEN 11 = DS = 00; END CASE; END PROCESS; END ONE; -- 一位二进制全减器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY F_SUBER IS PORT ( X, Y : IN STD_LOGIC; SUB_IN : IN STD_LOGIC; DIFFR : OUT STD_LOGIC; SUB_OUT : OUT STD_LOGIC); END F_SUBER; ARCHITECTURE BEHAV OF F_SUBER IS COMPONENT H_SUBER IS PORT ( X, Y : IN STD_LOGIC; DIFF : OUT STD_LOGIC; S_OUT : OUT STD_LOGIC ); END COMPONENT; SIGNAL A, B, C : STD_LOGIC; -- 元件之间的连线，DIFF-X, S_OUT-或门, S_OUT-或门 BEGIN U1 : H_SUBER PORT MAP (X = X, Y = Y, DIFF = A, S_OUT = B); U2 : H_SUBER PORT MAP (X = A, Y = SUB_IN, DIFF = DIFFR, S_OUT = C); SUB