chapt_02.pptVIP

Chapter 2: IA-32 Processor Architecture Chapter Overview General Concepts IA-32 Processor Architecture IA-32 Memory Management Components of an IA-32 Microcomputer Input-Output System General Concepts Basic microcomputer design Instruction execution cycle Reading from memory How programs run Basic Microcomputer Design clock synchronizes CPU operations control unit (CU) coordinates sequence of execution steps ALU performs arithmetic and bitwise processing Clock synchronizes all CPU and BUS operations machine (clock) cycle measures time of a single operation clock is used to trigger events Whats Next General Concepts IA-32 Processor Architecture IA-32 Memory Management Components of an IA-32 Microcomputer Input-Output System Instruction Execution Cycle Fetch Decode Fetch operands Execute Store output Multi-Stage Pipeline Pipelining makes it possible for processor to execute instructions in parallel Instruction execution divided into discrete stages Pipelined Execution More efficient use of cycles, greater throughput of instructions: Wasted Cycles (pipelined) When one of the stages requires two or more clock cycles, clock cycles are again wasted. Superscalar A superscalar processor has multiple execution pipelines. In the following, note that Stage S4 has left and right pipelines (u and v). Reading from Memory Multiple machine cycles are required when reading from memory, because it responds much more slowly than the CPU. The steps are: address placed on address bus Read Line (RD) set low CPU waits one cycle for memory to respond Read Line (RD) goes to 1, indicating that the data is on the data bus Cache Memory High-speed expensive static RAM both inside and outside the CPU. Level-1 cache: inside the CPU Level-2 cache: outside the CPU Cache hit: when data to be read is already in cache memory Cache miss: when data to be read is not in cache memory. How a Program Runs Multitasking OS can run multiple programs at the same time. Multiple threads of execution within the s