宽频带数字锁相环xx（Wideband digital phase-locked loop XX）.docVIP

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宽频带数字锁相环xx（Wideband digital phase-locked loop XX）.doc

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宽频带数字锁相环xx（Wideband digital phase-locked loop XX）

宽频带数字锁相环xx（Wideband digital phase-locked loop XX） Design of wideband digital phase-locked loop and Implementation Based on FPGA Time: 2007-03-02 10:48:00 source: World of electronic products: Li Xiaodong, Xian Polytechnic University Abstract: This paper briefly introduces the realization of all digital phase-locked loop in FPGA (DPLL) principle and method of fast recovery to solve the problem of clock synchronization in synchronous serial data communication is not stable; and introduces the method and process of ultrabroad bandwidth digital phase-locked ring capture controllable modulus divider to achieve the. Keywords: DPLL; FPGA; digital loop filter; clock recovery; wideband Introduction Digital phase locked loop (DPLL) technology has been widely used in many fields, such as digital communications, radio electronics and so on. Compared with the traditional analog circuit PLL, DPLL has the advantages of high accuracy, free from the influence of temperature and voltage, adjustable loop bandwidth and central frequency, and easy construction of high order pll. With the development of integrated circuit technology, not only can the monolithic integrated phase locked loop with higher frequency be produced, but also the whole system can be integrated into a chip. In the communication circuit based on FPGA, the full digital phase-locked loop can be embedded into FPGA as a function module to form an on-chip phase-locked loop. The data transmission between the general synchronous serial port communication mode synchronous serial port in addition to the data line must also have a special synchronous clock line, this connection not only need to add a line, synchronization performance is affected by the environment is larger. The digital phase locked loop (PLL) can recover the bit synchronization clock from the serial bit stream data. Thus, only one data line between the serial ports can receive synchronous serial data, thus simplifying the interface relationship of the serial