基于fpga高速时间交织adc校准与研究-集成电路工程专业论文.docxVIP

摘 摘 要 万方数据 万方数据 摘 要 随着数字全球化蓬勃发展，数字信号处理技术在宽带通信、计算机、数字雷 达、测量仪器等领域得到广泛应用。模拟数字转换器作为数字信号处理重要接口， 其向着高速度、高精度、超宽带发展。由于每种工艺的带宽的限制，单片单工艺 的模数转换器转换速率几乎已经达到极限。 多通道时间交织 ADC 结构成为突破速度瓶颈的一种重要途径，其以较低速子 ADC 并行工作实现更高的采样率。然而，通道间存在的失调失配、增益失配、采 样时刻偏差等限制了多通道时间交织 ADC 的性能，需要对这些失配进行校准。 本文具体内容如下： 1、建立了包含失调失配、增益失配、时钟失配的多通道时间交织 ADC 失配 模型，从理论上分析了失配对 ADC 性能的影响； 2、在现有研究的基础上，完成了三种类型的失配误差估算算法及仿真验证， 并提出了基于 FPGA 的数字模拟混合校正方案； 3、鉴于 FPGA 可编程灵活的特点，基于 FPGA 设计了 3Gsps 8bit 双通道时间 交织 ADC 系统，由 FPGA 实现了三种类型失配的实时处理。文中也对其他关键电 路进行了研究，如时钟分配电路、高速接口、高速数据采集、信号完整性等； 4、经过测试，相对于校正前，系统的无杂散动态范围(SFDR)提升了约 20dBc， 信噪比（SNR）提升了约 10dBc，有效位数（ENOB）提升了约 1bit。 关键词：模数转换器 时间交织 校准 时钟分配 信号完整性 Abst Abstract 万方数据 万方数据 Abstract With the rapid development of digital globalization, digital signal processing technology is widely used in wideband communication, computer, digital radar, measurement, instrument and many other fields. As a kind of interface circuit of great importance in digital signal processing, analog-to-digital converter(ADC) develops towards high speed, high resolution and ultra broadband. Due to the bandwidth of each process is limitied, the speed of single ADC almost reached its limits. Multi-channel time-interleaved ADC becomes an important way to break the speed bottleneck with lower speed sub-ADC operating in parallel to achieve a higher sampling rate. However, the mismatch between channels such as offset mismatch, gain mismatch and sample-time errors limits the multi-channel time-interleaved ADC performance, which needs to be calibrated. Details of this paper are as follows: A model was set for the mismatch of multi-channel time-interleaved ADC and a theoretical analysis was accomplished to see the effect of offset mistmatch, gain mismatch, sample-time errors on the performance of ADC. On the basis of existing reserch, this paper realized three kinds of mismatch error estimation algorithm and completed the simulation and validation. At the same time, a solution using digital-analog correction based on the FPGA was adopt