侯代彬的论文.docxVIP

摘要 在传统的硬件电路设计屮，设计者总是根据系统的具体要求，选择市场上能 够买到的逻辑元件、器件，来构成所要求的逻辑电路，从而完成系统的硕件设计。 这种自下至上选择通用元、器件来构成系统硕件电路的方法是目前广大电子工程 师所熟悉和掌握的一种传统的设计方法。 本课题结合工程应用，设计一种完全基于FPGA的定时器电路，实现定时器的 功能。文屮主耍把定时器分成控制器模块、周期模块、分频电路等模块，再把各 个模块进一步进行细分，运用VHDL编程语言，对各个模块进行语言编程设计电路, 并且进行结果仿真校验。最后进行电路连接，以达到预期的定时器功能，具冇时 分秒计数功能， 通过该课题，使我对可编程硬件电路的设计和制作得到全面的锻炼和实践， 同时也深入了解了数字电路的设计方法，捉高对VHDL语言的变成运用，增强了我 的工程开发和设计能力。 关键词：FPGA,定时器，控制器模块，周期模块 Abstract In traditional hardware circuit design, designers always according to the systems specific requirements, choose the market can buy logic components, components, to form required logic circuit, thus completing system hardware design. This from the first choice general yuan, devices to constitute the system hardware circuit method is currently general electronic engineers are familiar with and acquired a traditional design method ? This topic combining engineering application, designs a kind of timer circuit of complete according to FPGA, realizing the function of timer. The research divides the time into control module , cycle module ,and frequency circuit module , controlling key parts and so on, then taking each block more precise, using VHDL programmable language, to each the block carry on language plait distance design circuit, and carry on result in order to check. Last taking circuit with connecting, in order to attain to expectant function, having counting function of hour minute second , According to the topic, it is believed that it takes me important experience through to do design and creation programmable hardware circuit, also having a in?depth understanding to numeral design method of circuit, improving usage of VHDL language, strengthen engineering of development and design ability of my. Keywords: FPGA，timer, control module, cycle module 目录 TOC \o 1-5 \h \z 要 错 误！未定义书签。 Abstract 错误！未定义书签。 \o Current Document 目录 错 误！未定义书签。 \o Current Document 第一章概念简要 1 第二章世界集成电路技术的发展规律 \o Current Document 第三章设 计 流 程 与 功 能 错误！未定义书签。 \o Current Document J.3.1现代数字系统的设