半导体制造学-元件技术.pptVIP

VDD = + 3.0 V 閘極開路 (沒有電荷) 燈泡 (沒有導通) 源極 汲極 p型矽基板 n+ n+ 閘極 VGG = + 0.7 V S1 nMOS電晶體偏壓電路 圖 3.16 nMOS電晶體導通模式 S1 IDS VDD = + 3.0 V 正電荷 燈泡 e- e- e- + + + + + + + + + + + + + + + + + + 源極 汲極 p型矽基板 閘極 n+ n+ 電洞 VGG = + 0.7 V 圖 3.17 n通道MOSFET的特性曲線 圖 3.18 600 500 400 300 200 100 0 VGS = +5V VGS = +4V VGS = +3V VGS = +2V VGS = +1V 0 1 2 3 4 5 6 汲極－源極電壓，VDS (V) 飽和區 線性區 汲極電流IDS (?A) * * * There are two categories of MOS FETs -- the PMOS FET and the NMOS FET. Note the symbols and physical structures of these transistors. To begin with the substrates for the two transistors are of opposite polarity. In addition the PMOS device is based on a p+ diffused source and drain regions, while in the NMOS, these regions are doped n+. When each transistor is operational a channel of charged carriers is created between the respective s-d regions. For the PMOS transistor, this channel is referred to as the p-channel, while the n-channel designation is used for the NMOS transistor. There’s more to come about the channels in the next few slides. * If the FET is to work as an electronic switch, we would expect to obtain a conductive path between the source and drain of the device. A battery of 3 volts is connected to a small lamp by way of external wires. If the gate has no form of electrical charge on it, there is no electric field created between the gate and the substrate. Thus, the open gate results in an open non-conductive channel between the source and drain regions. The lamp remains in a non-conductive state. * A small input voltage at the gate is all that is needed to turn on the transistor. This voltage (Vgs) is externally connected between the gate and the source of the transistor. When increased from zero volts to a point called the “threshold voltage, Vth”, electrical current (Ids) starts to flow through the output of the transistor. This is due to the positive charge (