Allegro只给VIA或pin加背钻属性操作指导.pdfVIP

Allegro只给VIA或pin加背钻属性操作指导

Allegro支持只给孔加背钻属性，除了孔，pin也是可以的，具体操作步骤

如下

1.选择Edit-Property命令

2.Find选择Net

3.选择需要背钻的网络添加背钻属性，点击OK

4.设置下背钻参数

5.选择背钻种类，top钻选择top，bottom钻选择bottom

6.把需要背钻的pin加上不背钻的属性，find选择pins

7.选择不需要背钻的pin，添加Backdrill_Exclude属性

8.放出背钻表格

9.选择includebackdrill，点ok

10.可以看到只输出了孔的背钻，pin没有做背钻

11.如果只想给pin背钻，不想给孔背钻，操作也是一样的，加属性的时候选择

Vias

12.给孔加上添加Backdrill_Exclude属性

13.输出表格，可以看到指输出了pin的背钻

Thissectionisdescribewhatthefunctionallegrohave,helpfully

couldletuserknowmoreaboutallegro

AllegroDesignandAnalysisincludesdesignauthoring

PCBlayoutandLibraryandDesignDataManagement

With.Itcanensuretheend-to-enddesignofPCBwithhighqualityand

efficiency

Realizesmoothdatatransferbetweentools,shortenPCBdesigncycle,

andshortenproduct

Markettime

1.Designauthoring

Provideaflexiblelogicconstraintdrivenflow,managementdesign

rules,networkhierarchy,

Busanddifferentialpair.

1.1.1Mainfeaturesandfunctions

Throughhierarchicalanddesignderivationfunction,improvethe

originalofcomplexdesign

Mapeditingefficiency.

PowerfulCIShelpsusersquicklydeterminepartselectionand

acceleratedesignflow

Andreduceprojectcost.

1.2.1Mainfeatures

SchematicdesignersandPCBdesignengineerscanworkinparallel.

Advanceddesignefficiencyimprovesfunctions,suchascopyingthe

previousschematicdesignSelectmultiplexingwithorbypage.

Seamlessintegrationintopresimulationandsignalanalysis.

1.2.2MainFunctions

ProvideschematicdiagramandHDL/Verilogdesigninput.

Assignandmanagehigh-speeddesignrules.

Supportnetclasses,buses,extensionnetworksanddifferentialpairs.

Powerfullibrarycreationandmanagementfunctions.

Allowssynchronizationoflogicalandphysicaldesigns.

Realizemulti-userparalleldevelopmentandversioncontrol.

Preintegrationsimulationandsignalanalysis.

Supportcustomi