集成电路设计—时序逻辑电路设计.pptVIP

* 7-5 时钟控制寄存器C2MOS ——时钟偏差不敏感方法 “Keepers” can be added to make circuit pseudo-static 主从式； 正沿触发； CLK=0时 X=D求值，从级维持（高阻态）； CLK=1时 相反。 只要时钟边沿的上升和下降时间足够小，对时钟重叠不敏感。 * Insensitive to Clock-Overlap M 1 D Q M 4 M 2 0 0 V DD X M 5 M 8 M 6 V DD (a) (0-0) overlap M 3 M 1 D Q M 2 1 V DD X M 7 1 M 5 M 6 V DD (b) (1-1) overlap * 7-6 真单相时钟寄存器（True Single Phase Clock Register） Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1) 无时钟重叠； 减少时钟负载。 * Including Logic in TSPC AND latch Example: logic inside the latch 可嵌入逻辑功能。 * TSPC Register CLK=0 X=反相的D， Y预充电， Q维持； CLK=1 X高阻， Y = X的反相， Q= Y。 * Pulse-Triggered Latches Master-Slave Latches D Clk Q D Clk Q Clk Data D Clk Q Clk Data Pulse-Triggered Latch L1 L2 L Ways to design an edge-triggered sequential cell: * Pulsed Latches * 7-7 流水线（Pipelining） Reference Pipelined 寄存器传播延迟 寄存器建立时间 组合逻辑最坏延迟 * Latch-Based Pipeline * 7-8 非双稳态时序电路Non-Bistable Sequential Circuits Schmitt Trigger Monostable Trigger Astable Multivibrators VCO * Schmitt Trigger 对于缓慢的输入，快速翻转的输出响应； VTC正向、负向变化的输入信号有不同的阈值； 滞回电压为其差； 用于提高抗干扰能力，减少振铃现象。 In Out V in V out V OH V OL V M– V M+ * Noise Suppression using Schmitt Trigger * Latches vs Flipflops Latches level sensitive circuit that passes inputs to Q when the clock is high (or low) - transparent mode input sampled on the falling edge of the clock is held stable when clock is low (or high) - hold mode Flipflops (edge-triggered)一般指触发器 edge sensitive circuits that sample the inputs on a clock transition positive edge-triggered: 0 ? 1 negative edge-triggered: 1 ? 0 built using latches (e.g., master-slave flipflops) * Latch versus Register Latch stores data when clock is low Register stores data when clock rises D Clk Q Clk D Q D Clk Q Clk D Q Transparent * 7-2 锁存器（Latches） 类型 Latch-Based Design 时间定义与约束 改变输出 多路开关型锁存器 * 类型 * Latch-Based Design— for sequential N latch is transparentwhen f = 0 P latch is transparent when f = 1 P Latch Logic Logic N Latch f * 时间定义（Timing Definitions ） t CLK t D