Turbo乘积码编译码算法研究及其FPGA实现信息与通信工程专业论文.docxVIP

Turbo乘积码编译码算法研究及其FPGA实现信息与通信工程专业论文.docx

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Turbo乘积码编译码算法研究及其FPGA实现信息与通信工程专业论文

哈尔 哈尔滨工业大学工学硕士学位论文 哈尔 哈尔滨工业大学工学硕士学位论文 - - PAGE IV - - - III - Abstract Channel decoding is one of the key technologies in wireless communication system,for well channel decoding can efficiently improve the system performance. Since turbo codes were introduced by Berrou in 1993, many papers on turbo coding have been published. In 1994, P.Ryndiah investigates Turbo Product Code. It is a kind of block code, of which sub-code is linear code. Its decoding method adopts SISO iterative, the same as Turbo code, so it is called Turbo Product Code. Turbo Product codes are efficient error correcting codes. The performance of Turbo Product codes is better than that of turbo codes in high rate condition in additive Gaussian White noise channel. The asymptotic performance of turbo product codes take advantages over that of turbo codes in high signal to noise ratio. This dissertation firstly analyzes the encoding theory of Turbo Product Codes. Its sub-code can be either two-dimension or multi-dimension, and they can be either identical or different. Commonly used sub-codes include extended Hamming code, RS code and BCH code. Its decoding method adopts SISO iterative algorithm, and commonly used decoding algorithm include Chase algorithm, Maximum Likelihood algorithm and cyclic pseudo-maximum likelihood algorithm, ect. Comparing these decoding algorithms, decoding complexity of the improved Chase algorithm is lower, and then analyzes and compares the function of existing decoding algorithm and improves them. At last, this paper analyzes the factors which can affect the decoding performance, and simulate them by Matlab and determine the decoding program. According to simulation results of SISO algorithm, we design the TPC decoder by FPGA and divide them into small modules according to the top-to-down design, and that makes then design more flexible. After that, simulates every module and synthesize them together, and then run it on stratix III series chip. The simulation results

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