并行计算机体系结构-lec1latency.pptVIP

PCA L16 Chp8.1 Wu Spring 04 ? USTC Parallel Computer Architecture 并行计算机体系结构 Lecture 17 PCA L16 Chp8.2 Wu Spring 04 ? USTC Overview ° Review of Lec15 ? 基于目录的高速缓存一致性协议 ? 放松的存储一致性模型 ° 通信与延迟 PCA L16 Chp8.3 Wu Spring 04 ? USTC A Cache Coherent System Must: ° Provide set of states, state transition diagram, and actions ° Manage coherence protocol ? (0) Determine when to invoke coherence protocol ? (a) Find info about state of block in other caches to determine action - whether need to communicate with other cached copies ? (b) Locate the other copies ? (c) Communicate with those copies (inval/update) ° (0) is done the same way on all systems ? state of the line is maintained in the cache ? protocol is invoked if an “access fault” occurs on the line ° Different approaches distinguished by (a) to (c) PCA L16 Chp8.4 Wu Spring 04 ? USTC Bus-based Coherence ° All of (a), (b), (c) done through broadcast on bus ? faulting processor sends out a “search” ? others respond to the search probe and take necessary action ° Could do it in scalable network too ? broadcast to all processors, and let them respond ° Conceptually simple, but broadcast doesnt scale with p ? on bus, bus bandwidth doesnt scale ? on scalable network, every fault leads to at least p network transactions ° Scalable coherence: ? can have same cache states and state transition diagram ? different mechanisms to manage protocol PCA L16 Chp8.5 Wu Spring 04 ? USTC Scalable Approach: Directories ° Every memory block has associated directory information ? keeps track of copies of cached blocks and their states ? on a miss, find directory entry, look it up, and communicate only with the nodes that have copies if necessary ? in scalable networks, communication with directory and copies is through network transactions ° Many alternatives for organizing directory information P1 Cache Memory Scalable Interconnection Network Comm. As